A guide to ethernet switch and phy chips pdf

Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V).

Fully compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification.

Start of Frame Detect for IEEE 1588 time stamp.

25-MHz or 125-MHz synchronized clock output.

Programmable MAC interface termination impedance.

16 programmable RGMII delay modes on RX/TX.

Meets EN55011 class B emission standards.

Extra low latency TX < 90 ns, RX < 290 ns.

parametric-filter Ethernet retimers, redrivers & mux-buffers.

parametric-filter Serial digital interface (SDI) ICs.

parametric-filter RS-485 & RS-422 transceivers.

parametric-filter Optical networking ICs.parametric-filter Multi-switch detection interface (MSDI) ICs.parametric-filter LVDS, M-LVDS & PECL ICs.parametric-filter IO-Link & digital I/Os.parametric-filter HDMI, DisplayPort & MIPI ICs.parametric-filter Circuit protection ICs.parametric-filter CAN & LIN transceivers & SBCs.parametric-filter Wireless connectivity.parametric-filter Switches & multiplexers.parametric-filter Microcontrollers (MCUs) & processors.parametric-filter Logic & voltage translation.Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure.Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations.Synopsys 112G Ethernet PHY IP Datasheet Synopsys 112G Ethernet PHY IP for Very Short Reach

Support for the Pulse-Amplitude Modulation 4-Level (PAM-4), Non- Return-to-Zero (NRZ) signaling, and independent, per-lane data rates allows ultimate flexibility to address a broad range of protocols and applications.Īrchitected for very short reach chip-to-chip or chip-to-module electrical channels, the ultra-low power 112G VSR PHY enables power efficient pluggable and near packaged 400GbE/800GbE electro-optical interfaces.Ĭombined with Synopsys' routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY IP products for fast and reliable SoC integration. The PHYs’ flexible layout maximizes bandwidth per die-edge by allowing the placement of square macros in a multi-row structure and along all edges of the die. The power efficient PHY offers orders of magnitude better BER performance for Long Reach chip to chip channels with two connecters and multiple media. Synopsys 112G LR-Max TX Exceeds IEEE & OIF Jitter Specs with Symmetrical Eyes with Excellent Horizontal & Vertical Opening

A guide to ethernet switch and phy chips pdf